About

Hi, I'm Aarfa Bano Sheikh.

I’m a Computer Engineering graduate student at North Carolina State University specializing in computer architecture, SoC design, and verification. I currently design CAD automation flows as a Front-End CAD Engineer Co-op at Skyworks Solutions in San Jose, building resilient verification infrastructure for mixed-signal SoCs. I’m actively seeking full-time roles starting May 2026 that push the limits of compute, parallelism, and silicon-aware software.

Raleigh, NC May 2026 start FPGA · ASIC · CAD automation
asheikh7@ncsu.edu LinkedIn

Currently orbiting

  • UVM-driven verification of Skyworks timing IP
  • YAML-driven regression automation & reporting
  • GPGPU microarchitecture research @ NCSU
  • Exploring AI copilots for verification teams
SystemVerilog UVMF Python CUDA Synopsys DC

Experience

Jun 2025 – Dec 2025 · San Jose, CA

Front-End CAD Engineer (Co-op)

Skyworks Solutions, Inc.

  • Accelerated SoC verification cycles by automating simulation setup, data analysis, and YAML-driven UVMF interfaces.
  • Built Jenkins-based regression orchestration and log-aware coverage tracking to scale nightly runs.
  • Enabled mixed-signal verification uplift with Questa VIQ adoption, training, and flow integration.
SystemVerilog UVMF Python Jenkins Questa
Sept 2020 – Jul 2024 · Bengaluru, India

Electrical Engineer II

Baxter Innovations & Business Solutions

  • Led component engineering and board redesign to extend medical device lifespan by 10+ years, covering qualification through reliability.
  • Migrated FPGA platforms from Altera to Microchip/Xilinx with full timing, power, and thermal closure.
  • Designed Spartan-6 valve driver logic in Verilog to achieve noise-free operation under strict safety constraints.
Verilog FPGA Vivado Thermal Analysis
May 2019 – Jul 2019 · Pune, India

R&D Intern

Knorr-Bremse Technology Center India

  • Developed and validated low-level drivers for Infineon Aurix TC233 MCU, improving bus reliability across I2C, SPI, and UART.
  • Hardened microcontroller communication for safety-critical rail systems.
C Embedded I2C/SPI/UART

Education

North Carolina State University

Master of Science · Computer Engineering

Aug 2024 – May 2026 · GPA 3.61/4
  • ASIC/FPGA Design · ASIC Verification
  • Advanced UVM · Microprocessor Architecture
  • Parallel Computers · Data-Parallel Processors (GPGPU)
  • Neural Networks

MKSSS’s Cummins College of Engineering for Women

B.Tech · Electronics & Telecommunication

Aug 2016 – May 2020 · GPA 9.08/10

Skills & Tooling

Programming Languages

C C++ Verilog SystemVerilog Python Tcl CUDA C++

ASIC / FPGA Toolchain

Synopsys DC Mentor Graphics Xcelium Vivado MATLAB

Architectures & Protocols

RISC-V GPGPU Cache Coherence (MESI/MOESI) AMBA (APB/AHB/AXI) PCIe I2C UART Ethernet

Platforms & Productivity

Linux/Unix Git Docker VS Code Jupyter Jira Jenkins Tableau Minitab Jama Perforce

Projects

Floating-Point Matrix Multiplier

Designed a Verilog floating-point matrix multiplier with SRAM buffering and FSM-based control leveraging DesignWare MAC modules for speed/area balance.

Verilog SRAM DesignWare Synopsys DC
GitHub Project →

Transformer Attention Accelerator

Built a synthesizable scaled dot-product attention accelerator with a 28-state FSM and parallel SRAM interfaces to optimize transformer workloads.

Verilog SRAM Timing Analysis
GitHub Project →

Cache & Memory Hierarchy Simulator

Developed a C++ simulator implementing LRU, write-back, and prefetch stream buffers to profile miss rates and traffic.

C++ LRU Architectural Modeling
GitHub Project →

Out-of-Order Superscalar Simulator

Created a cycle-accurate simulator featuring configurable pipeline depth, dynamic scheduling, and latency-aware performance metrics.

C++ Superscalar Microarchitecture
GitHub Project →

GPU Cache Optimization in GPGPU-Sim

Implemented profiling-based L1 cache bypass and evaluated LRU/FIFO strategies to improve IPC on cache-unfriendly kernels.

C++ GPGPU-Sim Cache Policy
GitHub Project →

Scalable 3D FFT with OpenMP

Delivered a 3D FFT with thread scaling and scheduling exploration to significantly reduce execution time on multi-core CPUs.

C++ OpenMP Parallelism
GitHub Project →

Functional Verification of I2C Multiple Bus Controller

Built a layered SystemVerilog UVM testbench covering Wishbone + I2C transactions with randomized stimulus and structured sequences.

SystemVerilog UVM Questa
GitHub Project →

Contact

Let’s architect resilient compute together.

I’m open to ASIC/FPGA design, CAD automation, and computer architecture roles beginning May 2026. Share some context, timelines, and success criteria—I’ll get back quickly.

Email asheikh7@ncsu.edu
LinkedIn /aarfa-b-sheikh
Location Raleigh, NC 27606
Resume